The present invention relates generally to the design of application-specific integrated circuits (ASICs). More specifically, but without limitation thereto, the present invention relates to introducing repeater buffers in a hierarchical design of an integrated circuit.
With integrated circuit designs that include a hierarchy of macros each containing one or more xe2x80x9cchildxe2x80x9d macro blocks, it is often necessary to add repeaters for distributing signals to multiple destinations at lower levels in the hierarchical design. Introducing repeaters into the hierarchical design creates problems in floor planning and routing that must be addressed in either electronic design automation (EDA) software or by the circuit designer.
In one aspect of the present invention, a method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan of a parent macro in a hierarchical circuit design; passing outline and pin locations from the initial floorplan from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan of the child macro in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing first physical constraints information from the child macro to the parent macro; determining an ideal location for a repeater in the common area in response to the first physical constraints information; passing second physical constraints information associated with repeater placement and routing in the parent macro that overlap the area of the child macro from the parent level to the child macro; and generating a complete physical implementation of the parent macro.
In another aspect of the present invention, a method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan of a parent macro in a hierarchical circuit design; passing outline and pin locations from the initial floorplan from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan of the child macro in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing first physical constraints information from the child macro to the parent macro; determining an ideal location for a repeater in the common area in response to the first physical constraints information; passing second physical constraints information associated with repeater placement and routing in the parent macro that overlap the area of the child macro from the parent level to the child macro; adjusting the repeater placement to a nearest non-reserved location in the child macro to generate a new repeater location in the child macro; passing the new repeater location from the child macro to the parent macro; excluding an area from an abstract representation of the child macro corresponding to the new repeater location to signify that the new repeater location is not owned by the child macro; adjusting the repeater placement in the parent macro to the new repeater location; and generating a complete physical implementation of the parent macro including the repeater placement inside the area excluded from the abstract representation of the child macro.